As computer systems migrate towards the use of sophisticated multi-stage pipelines and large SMP shared cache structures, the ability to debug, analyze, and verify the actual hardware becomes increasingly difficult, during development, test, and during normal operations. Today's technology employs such levels of integration within a single piece of silicon that interfacing with external test equipment can be inadequate. It is often desirable for testing to monitor complex events so that useful debug and performance information can be captured in a fast, unobtrusive manner during machine development. The prior art in the field relating to the present invention teach various approaches to monitoring events and capturing data which we will describe. Normally the prior art monitors predefined events, or uses hardware dedicated to a specific function. They have tended to count or sample the events, usually for the purpose of performance analysis or instrumentation. The monitored events are not of great scope and are generally hard wired in silicon, or programmed through field programmable gate arrays, a Processor Controller Element, the Operating System, or an external device which must be attached to the main computer system. For example U.S. Pat. No. 3,644,927 (issued to Greene) describes an event monitor for switches and relays. U.S. Pat. No. 4,022,978 (issued to Connell et al.) monitors communication traffic and counts events. U.S Pat. No. 4,821,178 (issued to Levin et al.) implements a Processor Controller Element (PCE) driven apparatus which performs instrumentation sampling on predefined events. U.S. Pat. No. 4,435,759 (issued to Baum et al.) describes an external hardware device for correlating hardware and software events primarily through the use of an address compare mechanism. U.S. Pat. No. 5,675,729 (issued to Mehring) provides a more sophisticated means of counting hard wired events using chained comparators performing boolean compares. IBM Technical Disclosure Bulletin entitled RISC Superscalar Pipeline Out-of-Order Statistics Gathering and Analysis (Vol. 37 NO. 04B April 1994) describes a system for monitoring instruction streams for a RISC microprocessor searching for out-of-order execution sequences. IBM Technical Disclosure Bulletin entitled Processor Performance Monitoring with Depiction of the Efficiency of Bus Utilization and Memory Accesses of Superscalar Microprocessor (Vol. 40 No. 01 January 1997) discloses an approach to analyzing whether the bus unit between the processor and storage has enough capacity to feed the processor efficiently. All of these prior publications gather instrumentation data and count occurrences of predefined events. However, none of them address the ability to capture data necessary to debug complex problems, since they are limited to the specific events that they are designed to monitor.
We note that there have been programmable event monitors such as U.S. Pat. No. 5,355,484 and in particular U.S. Pat. No. 5,237,684 (issued to Record et al.) which describes a software (operating system) event monitor and handler. In addition, U.S. Pat. No. 5,426,741 (issued to Butts et al.) monitors and counts events that are programmable via field programmable gate arrays. However, programming events is inadequate, and in our view there is a need for trace and debug capability, and real time direct access to the hardware.
U.S. Pat. No. 5,210,862 (issued to DeAngelis et al.) describes a way to monitor with hardware and for capturing debug data; however, the implementation relies on using addressable arrays to hold the target event being watched for. In large systems such as S/390 Enterprise Servers, typical fields to monitor such as addresses, commands, etc. are large and abundant. Therefore, any attempt to use the teachings of U.S. Pat. No. 5,219,0862 would require very large arrays. These are costly to implement since they must meet strict access times and incorporate Array Built-In Self Test (ABIST) structures for reliability. Furthermore, the patented idea is not well suited to monitoring multistage pipelines or complex event scenarios which require a more sophisticated controller for the trace array.